Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date         : Sun Apr 12 14:22:33 2026
| Host         : debian running 64-bit Debian GNU/Linux 13 (trixie)
| Command      : report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx
| Design       : system_wrapper
| Device       : xc7z020clg400-1
| Speed File   : -1
| Design State : Fully Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 40
+-----------+----------+-------------------------------------------------+------------+
| Rule      | Severity | Description                                     | Violations |
+-----------+----------+-------------------------------------------------+------------+
| TIMING-18 | Warning  | Missing input or output delay                   | 32         |
| XDCC-5    | Warning  | User Non-Timing constraint/property overwritten | 4          |
| RTGT-1    | Advisory | RAM retargeting possibility                     | 4          |
+-----------+----------+-------------------------------------------------+------------+

2. REPORT DETAILS
-----------------
TIMING-18#1 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[0] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#2 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[10] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#3 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[11] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#4 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[12] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#5 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[13] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#6 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[14] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#7 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[15] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#8 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[1] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#9 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[2] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#10 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[3] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#11 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[4] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#12 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[5] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#13 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[6] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#14 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[7] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#15 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[8] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#16 Warning
Missing input or output delay  
An input delay is missing on adc_dat_a_i[9] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#17 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[0] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#18 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[10] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#19 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[11] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#20 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[12] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#21 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[13] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#22 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[1] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#23 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[2] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#24 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[3] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#25 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[4] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#26 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[5] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#27 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[6] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#28 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[7] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#29 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[8] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#30 Warning
Missing input or output delay  
An output delay is missing on dac_dat_o[9] relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#31 Warning
Missing input or output delay  
An output delay is missing on dac_rst_o relative to clock(s) adc_clk_p_i
Related violations: <none>

TIMING-18#32 Warning
Missing input or output delay  
An output delay is missing on dac_sel_o relative to clock(s) adc_clk_p_i
Related violations: <none>

XDCC-5#1 Warning
User Non-Timing constraint/property overwritten  
A new XDC property IOSTANDARD on dac_pwm_o[0] overrides a previous user property.
New Source: /home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc (Line: 115)
Previous Source: /home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc (Line: 103)
Related violations: <none>

XDCC-5#2 Warning
User Non-Timing constraint/property overwritten  
A new XDC property IOSTANDARD on dac_pwm_o[1] overrides a previous user property.
New Source: /home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc (Line: 115)
Previous Source: /home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc (Line: 103)
Related violations: <none>

XDCC-5#3 Warning
User Non-Timing constraint/property overwritten  
A new XDC property IOSTANDARD on dac_pwm_o[2] overrides a previous user property.
New Source: /home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc (Line: 115)
Previous Source: /home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc (Line: 103)
Related violations: <none>

XDCC-5#4 Warning
User Non-Timing constraint/property overwritten  
A new XDC property IOSTANDARD on dac_pwm_o[3] overrides a previous user property.
New Source: /home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc (Line: 115)
Previous Source: /home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc (Line: 103)
Related violations: <none>

RTGT-1#1 Advisory
RAM retargeting possibility  
Identified 12 RAM32X1D primitives that could be retargeted to RAM32M. Retargeting will save approximately 4 memory LUTs and improve routability. These can usually be achieved using synthesis inference or XPMs. The memories are system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_0_0,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_10_10,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_11_11,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_12_12,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_13_13,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_14_14,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_15_15,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_1_1,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_2_2,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_3_3,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_4_4
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_5_5
Related violations: <none>

RTGT-1#2 Advisory
RAM retargeting possibility  
Identified 12 RAM32X1D primitives that could be retargeted to RAM32M. Retargeting will save approximately 4 memory LUTs and improve routability. These can usually be achieved using synthesis inference or XPMs. The memories are system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_0_0,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_10_10,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_11_11,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_12_12,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_13_13,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_14_14,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_15_15,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_1_1,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_2_2,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_3_3,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_4_4
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_5_5
Related violations: <none>

RTGT-1#3 Advisory
RAM retargeting possibility  
Identified 12 RAM32X1D primitives that could be retargeted to RAM32M. Retargeting will save approximately 4 memory LUTs and improve routability. These can usually be achieved using synthesis inference or XPMs. The memories are system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_0_0,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_10_10,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_11_11,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_12_12,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_13_13,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_14_14,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_15_15,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_1_1,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_2_2,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_3_3,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_4_4
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_5_5
Related violations: <none>

RTGT-1#4 Advisory
RAM retargeting possibility  
Identified 12 RAM32X1D primitives that could be retargeted to RAM32M. Retargeting will save approximately 4 memory LUTs and improve routability. These can usually be achieved using synthesis inference or XPMs. The memories are system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_0_0,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_10_10,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_11_11,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_12_12,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_13_13,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_14_14,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_15_15,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_1_1,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_2_2,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_3_3,
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_4_4
system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_5_5
Related violations: <none>


